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Remote-Junction Temperature-Controlled
Fan-Speed Regulator with SMBus Interface
ELECTRICAL CHARACTERISTICS (continued)
(V CC = +3V to +5.5V, V VFAN = +12V, T A = -40°C to +125°C, unless otherwise specified. Typical values are at V CC = +3.3V and
T A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Tach Input Transition Level
Tach Input Hysteresis
Current-Sense Tach Threshold
Current-Sense Tach Hysteresis
Fan Output Current
V VFAN = 12V
V FAN = 12V
250
10.5
190
20
0.3
V
mV
mA
mA
mA
Fan Output Current Limit (Note 3)
320
410
mA
Fan Output On-Resistance
R ONF
250mA load
4
?
SMBus INTERFACE: SMBDATA, ALERT , STBY , OVERT
Logic Input Low Voltage
Logic Input High Voltage
V IL
V IH
V CC = +3.0V to +5.5V
V CC = +3.0V
V CC = +5.5V
2.2
2.6
0.8
V
V
Input Leakage Current
Output Low Sink Current
I_leak
I OL
V IN = GND or V CC
V OL = 0.4V
-2
6
+2
μA
mA
Input Capacitance
Output High Leakage Current
C in
V OH = 5.5V
5
1
pF
μA
Serial Clock Frequency
Bus Free Time Between Stop
and Start Conditions
f SCL
t BUF
(Note 4)
0
4.7
100
kHz
μs
Start Condition Setup Time
4.7
μs
Repeat Start Condition Setup
Time
Start Condition Hold Time
Stop Condition Setup Time
Clock Low Time
Clock High Time
Data Setup Time
Data Hold Time
Receive SMBCLK/SMBDATA
Rise Time
Receive SMBCLK/SMBDATA
Fall Time
t SU:STA
t HD:STA
t SU:STO
t LOW
t HIGH
t SU:DAT
t HD:DAT
t R
t F
90% to 90%
10% of SMBDATA to 90% of SMBCLK
90% of SMBCLK to 10% of SMBDATA
10% to 10%
90% to 90%
90% of SMBDATA to 10% of SMBCLK
(Note 5)
50
4
4
4.7
4
250
0
1
300
μs
μs
μs
μs
μs
ns
μs
μs
ns
SMBus Timeout
t TIMEOUT
SMBDATA and SMBCLK time low for reset
of serial interface
25
40
ms
Note 1:
Note 2:
Note 3:
Note 4:
Junction Temperature = T A . This implies zero dissipation in pass transistor (no load, or fan turned off).
T RJ , Remote Temperature accuracy is guaranteed by design, not production tested.
Guaranteed by design. Not production tested.
The MAX6660 includes an SMBus timeout, which resets the interface whenever SMBCLK or SMBDATA has been low for
greater than 25ms. This feature can be disabled by setting bit 2 of the Fan Gain register at 16h/1Bh to a 1. When the timeout
is disabled, the minimum clock frequency is DC.
Note 5: Note that a transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of
SMBCLK’s falling edge.
_______________________________________________________________________________________
3
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